1. Field of the Invention
The present invention relates to a high-speed carry increment adding device for digital devices.
2.Description of the Prior Art
Generally, an adding device is a basic block of an arithmetic logic unit and is required to have a high-speed processing capability because it is an important factor of determining a performance of such a digital device.
As conventional adding devices, there have been proposed a carry lookaffead adding device, a carry skip adding device and a carry select adding device, which has a performance faster than the others in view of a construction except an improvement in circuitry.
Referring to FIG. 1, there is shown a block diagram of a conventional carry select adding device which performs 8-bit addition. As shown in this drawing, the conventional carry select adding device comprises three ripple carry adders (referred to hereinafter as RCAs) 11-13 and data selectors 14-17. The RCAs 11-13 are partitioned adders, each of which generates a plurality of partitioned sums and a partitioned carry in the unit of module of a given number of bits. Here, the partitioned adders receive 4 bit inputs to be added in the unit of module.
The RCA 11 of the first module receives 4 bit inputs a0b0-a3b3 and generates partitioned sums S0-S3 and a partitioned carry C1. Without waiting for generation of a "1" or "0" carry in the RCA 11 of the low-order module, the RCAs 12 and 13 of the high-order module add 4 bit inputs a4b4-a7b7 simultaneously.
Namely, the RCA 12 of the high-order module previously adds the 4 bit inputs a4b4-a7b7 with respect to the case where the partitioned carry 01 from the RCA 11 of the low-order module is "0". At the same time, the RCA 13 of the high-order module previously adds the 4 bit inputs a4b4-a767 with respect to the case where the partitioned carry C1 from the RCA 11 of the low-order module is "1". Then, each of the data selectors 14-17 selects one of corresponding ones of the partitioned sums from the RCAs 12 and 13 in response to the partitioned carry C1 from the RCA 11 to output a corresponding one of partitioned sums S4-S7. In this manner, the 8-bit addition is performed.
The total delay time of the adding device in FIG. 1 is the sum of a delay time of the RCA 11 of the low-order module and a delay time for which the outputs from the RCAs 12 and 13 of the high-order module are multiplexed in response to the partitioned carry C1 from the RCA 11.
Referring to FIG. 2, there is shown a block diagram of a conventional carry select adding device Which performs 16-bit addition. As shown in this drawing, the conventional carry select adding device comprises RCAs 21-27 and data 28-39 in the same manner as that in FIG. 1. Also, the carry select adding device comprises AND gates 40 and 42 and 0R gates 41 and 43 which provide select signals to the data selectors 32-39 of the subsequent modules in response to generated carries.
The total delay time of the adding device in FIG. 2 is the sum of a delay time of the RCA 21 of the lowest-order module and a multiplexing time of the RCAs 22-27 of the higher-order modules. In this connection, the carry select adding device can perform he addition operation at a very high speed.
In other words, the conventional carry select adding device transfers the carries by modularizing a given number of bits or a useful bit length, to make up for a drawback in the carry transfer by bits. As a result, the conventional carry select adding device has the high-speed processing capability.
However, the conventional carry select adding device has a disadvantage in that the carries being successively transferred in the unit of module are subjected to a restriction resulting from the multiplexing loads. Also, two RCAs are required in the unit of module, resulting in an increase i n an area of the adding device. Further, the carries are rippled in the unit of module. This results in a reduction in the operation speed as the bits to be processed are increased in number. For this reason, a dual verification is typically required in an existing floating point arithmetic. Also, the addition operation cannot be performed at the high speed with respect to the large number of bits such as, for example, 64 bits. In other words, in the case where the bits to be added are large in number, an improvement in the operation speed is accompanied with an increase in the design time and cost although it is enabled by a technique in circuitry or a manufacturing process,